Betekenis van:
bits per second

Werkwoord

Voorbeeldzinnen

1. Execution time 't' is expressed in microseconds, TP and "CTP" are expressed in millions of theoretical operations per second (Mtops) and WL is expressed in bits.
2. multiply Execution time 't' is expressed in microseconds, TP and "CTP" are expressed in millions of theoretical operations per second (Mtops) and WL is expressed in bits.
3. Where R' is the number of results per second, WL is the number of bits upon which the logic operation occurs, and 64 is a factor to normalise to a 64 bit operation.
4. Where R' is the number of results per second, WL is the number of bits upon which the logic operation occurs, and 64 is a factor to normalize to a 64 bit operation.
5. Execution time 't' is expressed in microseconds, TP and "CTP" are expressed in millions of theoretical operations per second (Mtops) and WL is expressed in bits. Outline of "CTP" calculation method
6. "Technology" according to the General Technology Note other than that specified in 3E001 for the "development" or "production" of "microprocessor microcircuits", "microcomputer microcircuits" and microcontroller microcircuits having a "composite theoretical performance" ("CTP") of 530 million theoretical operations per second (Mtops) or more and an arithmetic logic unit with an access width of 32 bits or more.
7. "Technology" according to the General Technology Note other than that specified in 3E001 for the "development" or "production" of "microprocessor microcircuits", "microcomputer microcircuits" and microcontroller microcircuits having a "composite theoretical performance" ("CTP") of 530 million theoretical operations per second (Mtops) or more and an arithmetic logic unit with an access width of 32 bits or more. Note: Decontrol note 2 to 3E001 also applies to 3E002. 3E003
8. Technical Note: The term "multi-layer structures" does not include devices incorporating a maximum of three metal layers and three polysilicon layers. 3E002 "Technology" according to the General Technology Note other than that specified in 3E001 for the "development" or "production" of "microprocessor microcircuits", "microcomputer microcircuits" and microcontroller microcircuits having a "composite theoretical performance" ("CTP") of 530 million theoretical operations per second (Mtops) or more and an arithmetic logic unit with an access width of 32 bits or more. Note: Decontrol note 2 to 3E001 also applies to 3E002. 3E003
9. "Digital computers" having a "composite theoretical performance" ("CTP") exceeding 28000 million theoretical operations per second (Mtops ); or 2. "Electronic assemblies" specially designed or modified for enhancing performance by aggregation of "computing elements" ("CEs") so that the "CTP" of the aggregation exceeds the limit in 4E001.b.1. Technical note on "Composite Theoretical Performance" ("CTP") Abbreviations used in this Technical Note "CE" "computing element" (typically an arithmetic logical unit) FP floating point XP fixed point t execution time XOR exclusive OR CPU central processing unit TP theoretical performance (of a single "CE") "CTP" "composite theoretical performance" (multiple "CEs") R effective calculating rate WL word length L word length adjustment * multiply Execution time 't' is expressed in microseconds, TP and "CTP" are expressed in millions of theoretical operations per second (Mtops) and WL is expressed in bits. Outline of "CTP" calculation method "CTP" is a measure of computational performance given in Mtops. In calculating the "CTP" of an aggregation of "CEs" the following three steps are required: 1. Calculate the effective calculating rate R for each "CE"; 2. Apply the word length adjustment (L) to the effective calculating rate (R), resulting in a Theoretical Performance (TP) for each "CE"; 3. If there is more than one "CE", combine the TPs, resulting in a "CTP" for the aggregation. Details for these steps are given in the following sections.